1. Technical Field
The present disclosure relates generally to information processing systems and, more specifically, to structured exception handling for user-level threads in a multi-threading system.
2. Background Art
In order to increase performance of information processing systems, such as those that include microprocessors, both hardware and software multi-threading techniques have been employed. Increasingly, multi-threading is supported in hardware. For instance, in one approach, processors in a multi-processor system, such as a chip multiprocessor (“CMP”) system, may each act on one of the multiple software threads concurrently. In another approach, referred to as simultaneous multi-threading (“SMT”), a single physical processor is made to appear as multiple logical processors to operating systems and user programs. For SMT, multiple software threads can be active and execute simultaneously on a single processor without switching. That is, each logical processor maintains a complete set of the architecture state, but many other resources of the physical processor, such as caches, execution units, branch predictors, control logic and buses are shared. For SMT, the instructions from multiple software threads thus execute concurrently on each logical processor.
For a system that supports concurrent execution of software threads, such as SMT and/or CMP systems, an operating system application may control scheduling and execution of the software threads on thread execution resource(s). However, other thread execution resources that are not controlled by the operating system may also be available to a programmer and may be controlled by user-level code. Common operating systems do not provide for data structures to maintain local data for user-level threads that may execute on such resources.